1. Technical Field
The present invention generally relates to computer systems and in particular to techniques for modeling variables in subprograms of Hardware Description Language programs executed in computer systems.
2. Description of the Related Art
A Hardware Description Language (HDL) is generally used in simulation programs for modeling the temporal behaviour and/or spatial circuit structure of electronic devices and systems. Syntax and semantics of HDL programs (i.e., programs written in HDL) include notations for expressing time and concurrency, which are the primary attributes of the electronic hardware.
A HDL program is designed to implement the underlying semantics of the language statements and provides hardware designers with the ability to model a piece of electronic hardware before the hardware is implemented physically. Commonly used HDLs are VHDL developed for modeling field-programmable arrays (FPAs) and application-specific circuits (ASICs) and the Verilog, which is mostly used for modeling electronic systems.
Both VHDL and Verilog support subprograms used for describing reusable portions of the designs being simulated. However, present semantics of the subprograms does not allow a designer to infer, during execution of a respective subprogram, the content of memory associated with values of variables used in the subprogram. Such drawbacks of these HDLs limit the subprograms to description of computational logic devices and do not allow simulation of sequential circuits.